The bladeRF 2.0 micro xA4 is the next generation Software Defined Radio (SDR) offering a frequency range of 47MHz to 6GHz, 61.44MHz sampling rate, and 2×2 MIMO streaming. Packed into a small form factor, the bladeRF 2.0 micro was designed for high performance as well as mobile applications. Through libbladeRF the bladeRF 2.0 micro is compatible with GNURadio, GQRX, SDR-Radio, SDR#, gr-fosphor, SoapySDR, and more on Windows, Linux and macOS.
The RF shield cap protects sensitive RF components from Electromagnetic Interference (EMI) and provides additional thermal dissipation, allowing the bladeRF 2.0 micro to operate in challenging environments.
All of the RF SMA ports are capable of providing power over bias-tee circuitry to wideband amplifiers and pre-amps. Power to bias-tee peripherals is fully software controllable, providing maximal operational flexibility. Currently, the official bias-tee peripherals include the BT-100, a wideband power amplifier for TX, and the BT-200, a wideband low noise amplifier for RX.
At the core of the bladeRF 2.0 micro is the latest generation Cyclone V FPGA from Intel (formerly Altera). The xA4 features a 49KLE FPGA of which about 38KLE are available and user programmable. Optionally, to accelerate modems in HDL and for additional FPGA space, consider the bladeRF xA9, which features the largest-in-class FPGA of any single SDR with 301KLE of which about 294KLE are available and user programmable.
An advanced clocking architecture allows the bladeRF 2.0 micro to receive and provide its 38.4MHz fundamental clock from and to other devices. Additionally, an on-board PLL allows the bladeRF 2.0 micro to tame its VCTCXO to a 10MHz reference signal. The xA4 features a highly accurate and stable oscillator. The on-board DAC sets the frequency trim of the oscillator to a factory calibrated value.
The Power Distribution Network (PDN) of the bladeRF 2.0 micro features an intricate combination of low noise and high efficiency switch mode and linear power regulators. While the bladeRF 2.0 micro can be run solely from USB bus power, an external power source can be supplied to ensure maximal linear performance of bias-tee peripherals. The PDN features an auto selection and hold-over circuitry to optimize power draw between USB bus and external DC power.
The bladeRF 2.0 micro can run in headless without needing to be connected to a PC or SBC. The on-board flash is large enough to hold any size FPGA image for the xA4.
